Floorplanning

This is the first major step in getting your layout done, and for me this is the most important one.Your floorplan determines your chip quality.At this step, you define the size of your chip/block, allocates power routing resources, place the hard macros, and reserve space for standard cells.Every subsequent stage like placement, routing and timing closure is dependent on how good your foorplan is. In a real time design, you go through many iterations before you arrive at an optimum floorplan.

1. Core Boundary
   Floorplan defines the size and shape of your chip/block. A top level digital design will have a rectangular/square shape, whereas a sub block may have rectangular or rectilinear shapes. Core boundary refers to the area where you will be placing standard cells and other IP blocks. You may have power routing spaces allocated outside the core boundary. For a full chip, you will also have IO buffers and IO pads placed outside the core boundary.
   In your PnR tool, floorplanning can be controlled by various parameters:
   • Aspect ratio: This is the ratio of height divided by width and determines whether you get a square or rectangular floorplan. An aspect ratio of 1 gives you a square floorplan.
   • Core utilization
     Core utilization = (standard cell area+ macro cells area)/ total core area
     A core utilization of 0.8 means that 80% of the area is available for placement of cells, whereas 20% is left free for routing.
   • Boundary: You can specify a boundary and ask the tool to honour it. This can come in handy when you have an existing boundary from a previous version.When you specify Boundary as the control parameter, both aspect ratio and core utilization are irrelevant. The tool gives you a report of the utilization for the current boundary specified.
   1 2 3 4 5 6 7 8

   read_pin_pad_physical_constraints ./pins.tdf set_fp_pin_constraints -hard_constraints {layer location}  -block_level read_def ./boundary.def create_floorplan -control_type boundary -start_first_row -flip_first_row \                  -left_io2core 10 -bottom_io2core 10 \                  -right_io2core 10 -top_io2core 10
2. IO Placement/Pin placement
   If you are doing a digital-top design, you need to place IO pads and IO buffers of the chip.Take a reactangular or square chip that has pads in four sides.To start with, you may get the sides and relative positions of the PADs from the designers. You will also get a maximum and minimum die size according to the package you have selected. To place IOs, I use a perl script to place them once I decide on my chip size.
   If you are doing a digital block, you will need to place pins around the boundary to connect to the higher level routing. Cadence tools can use a DEF file or a custom floorplan file to do this. ICC can read in a DEF or a pin placement file to do the SAME.
   DEF extract:
   DESIGN my_design_lib;
UNIT DISTANCE MICRON 1000 ;
DIEAREA ( 0 0 ) ( 1914800 1150100 ) ;
   PINS 550 ;
   - sel[1] + NET sel[1]
   + DIRECTION INOUT
   + LAYER MET3 ( 0 0 ) ( 500 500 )
   + PLACED ( 0 265900 ) N ;
   ....
   END PINS;
   END DESIGN;
3. Macro placement
   Once you have the size & shape of the floorplan ready and initialized the floorplan, thereby creating standard cell rows, you are now ready to hand place your macros. Do not use any auto placement, I have not seen anything that works. Flylines in your tool will show you the connection between the macros and standard cells or IOs.
   1. Use flylines and make sure you place blocks that connects to each other closer
   2. For a full-chip, if hard macros connect to IOs, place them near the respective IOs
   3. Consider the power straps while placing macros. You can club macros/memories
   4. Creating Power Rings and Straps
      This is a topic worthy of its own article, and I will get to arriving at the number and width of power rings&straps at another post. Let me just now touch upon how to generate the power rings using ICCompiler.
      At this stage, you decide on the trunks that supply power to the core. You also have to make sure that all the hard macros have sufficient rings/straps around it to hook into the PG trunks. As usual, a robust power structure will take iterations and IR drop analysis at a later stage, but a close approximation can be arrived at the initial stages.
      create_rectangular_rings, create_rectilinear_rings and create_power_straps are some commands in ICCompiler that will let you create the power network.